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SoC Software Architect

Dubai, United Arab Emirates
Full time
On-site

Job description

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About Us
We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.
Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.
As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.
Your Mission
As a SoC Software Architect, you will define the chip architecture from a software and workload perspective — bridging AI applications, system software stacks, and compilers with the underlying SoC and multi-die microarchitecture. You will focus on data and computation flows, memory/cache hierarchies, and multi-die/chiplet architectures, translating real-world AI use cases into clear hardware and system-software requirements. You will influence boot flows, BSPs, drivers, virtualization, and security through requirements and design reviews, while dedicated teams own their detailed implementation.
Responsibilities
  • Workload-driven SoC definition with RTL collaboration: analyze AI workloads and system use cases (training, inference, scale-out, multi-tenant), translate them into SoC-level requirements for compute, memory, interconnect, and RAS, and iterate with RTL/SoC architects to balance programmability, performance, and PPA.
  • Data, computation, and multi-die flow architecture: design end-to-end data and control flows across host, PCIe/CXL, on-chip interconnects, accelerators, memory, and network interfaces, including how multi-die/chiplet configurations are represented to system software (devices, ranks, topology, NUMA-like properties).
  • Memory and cache hierarchy co-design: analyze workload footprints, co-design memory/cache hierarchies and placement strategies, and define requirements for MMU/IOMMU, address translation, coherency, and QoS in collaboration with SoC vendors and internal silicon teams.
  • System-software contracts (firmware, drivers, runtimes): define software-architectural contracts between the SoC and firmware, Linux drivers, and user-space runtimes/collective libraries—covering services, device models, queueing and DMA semantics, topology discovery, and error reporting—while leaving detailed implementation ownership to those teams.
  • Performance and observability architecture: establish key metrics, counters, traces, and telemetry paths needed to size architectures, diagnose bottlenecks, and validate performance; work with RTL, performance, and system-software engineers to ensure the implemented micro-architecture and software stack together meet latency, bandwidth, and scalability targets.
  • Cross-functional collaboration and documentation: write precise software-architectural specs and interface contracts, and lead or participate in design reviews with SoC, firmware, kernel/driver, runtime, and security teams to ensure a coherent end-to-end architecture.
Requirements
  • Bachelor's or Master's in Computer Engineering, Electrical Engineering, Computer Science, or related field.
  • 7+ years in SoC, embedded, or system software architecture, with a strong focus on the interaction between hardware and system software.
  • Experience with AI accelerators or GPU-style compute platforms, or close involvement in an AI ASIC/accelerator project, with a solid grasp of how AI workloads stress compute, memory, and interconnect.
  • Firm grounding in memory hierarchy (MMU/IOMMU, page tables, cache coherence protocols, prefetch/QoS) and interconnects (AMBA AXI/CHI/NoC or similar fabrics).
  • Solid Linux systems knowledge (memory and I/O models, NUMA, drivers, and how user space interacts with the kernel and hardware).
  • Deep understanding of the compiler-to-hardware interface: how graph-level optimizations (fusion, tiling, layout, quantization) translate into SoC and memory hierarchy requirements.
  • Understanding of boot chains, BSPs, and low-level firmware for multi-core SoCs, with the ability to review designs and requirements and collaborate effectively with dedicated firmware/boot teams.
  • Familiarity with platform security concepts (secure boot, key provisioning, TEEs, isolation) and the ability to work closely with security specialists, even if you are not the primary security architect.
  • Proficiency in C/C++ and scripting (Python, Bash); comfort with performance analysis tools, profilers, and traces across the HW/SW boundary.
  • Experience with emulation/FPGA/QEMU or similar platforms and correlating pre-silicon models to silicon behavior.
  • Excellent cross-functional communication and documentation skills; ability to lead design reviews and drive alignment with internal and external partners.
Preferred Qualifications (Nice-to-Haves)
  • Deeper experience with graph-compilation stacks (TVM, XLA, Glow) or GPU compute (CUDA/ROCm/OpenCL), including performance tuning and low-level debugging.
  • Hands-on with compiler passes (LLVM/MLIR), quantization, kernel fusion, tiling, and memory layout transforms for AI workloads.
  • Knowledge of power/perf management (DVFS, residency models, idle states) and system-level QoS for mixed AI/IO workloads.
  • Experience with secure elements/TPMs, attestation flows, and supply-chain security for firmware.
  • Familiarity with co-simulation workflows and performance modeling tools.
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