Verification Engineer
Dubai, United Arab Emirates
Full timeOn-site
Job description
Your Mission
Own the end-to-end verification of critical ASIC subsystems—from compute pipelines and high-speed I/O to interconnects and multi-die coherency. You’ll architect UVM environments and golden reference models, turn specs into assertions and checkers, drive coverage to closure, and tie in emulation/FPGA and SW-in-the-loop to catch bugs before tape-out. This is where one missed corner case can cost millions—finding it early keeps our AI silicon on schedule and on target.
Responsibilities
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Own block-to-subsystem verification: author verification plans from specs, define stimulus/coverage strategy, and deliver sign-off with data (functional/code/assertion coverage).
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Build scalable UVM environments: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI), protocol checkers, and reusable components.
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Exercise real workloads: co-sim with firmware/drivers, run emulation/FPGA prototypes, and correlate performance/behavior with architectural models.
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Apply assertions & formal: write SVA, run formal where appropriate (protocol/liveness/safety), and integrate results into overall coverage.
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Close quality gates: lint/CDC/RDC verification collaboration, gate-level/reset/power-up scenarios, low-power (UPF) intent checks.
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Harden regressions: own CI pipelines, randomized/constrained tests, triage failures, root-cause with RTL/design, and track fixes to closure.
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Interface & document: keep specs, test plans, coverage dashboards, and bug reports clear for Architects, RTL, Firmware/Drivers, and DFT/PD teams.
You'll Collaborate With
Silicon architects (clarifying intent and performance targets), RTL designers (debug and ECOs), firmware and Linux driver teams (HW/SW co-verification), performance architects (workload traces and counters), and EDA/CAD (flows, regressions, metrics) to ensure first-pass silicon success.
Minimum Qualifications
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7+ years in ASIC/SoC verification with SystemVerilog/UVM (ownership from test plan to sign-off).
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Strong command of constrained-random stimulus, scoreboarding, coverage-driven verification, and SVA.
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Hands-on with major simulators (e.g., VCS/Questa/Xcelium) and regression/CI tooling.
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Familiarity with standard protocols (AMBA, AXI, APB, AHB) and industrial VIPs
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Experience verifying complex IP/subsystems (at least one of: multi-core compute, NoC/coherency, high-speed I/O like PCIe, Ethernet 100/400G, HBM/DDR, UCIe).
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Proficient in scripting for automation (Python/TCL/Make) and building reusable verification components.
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Solid understanding of SoC fundamentals: resets, clocking, CDC/RDC, back-pressure/flow control, performance counters.
Preferred (Nice-to-Haves)
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Emulation/FPGA prototyping (Palladium/Zebu/Veloce; Xilinx/Intel) and SW-in-the-loop setups.
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Formal verification experience (JasperGold/VC Formal) and assertion methodology leadership.
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DFT/DFD awareness and post-silicon bring-up experience.
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Exposure to AI accelerator domains (systolic/dataflow, memory hierarchies, tiling) and traffic modeling.
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Experience building coverage dashboards and integrating verification metrics into CI/CD.
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Experience with C/C++/DPI for RTL Co-Simulation.